Vicom Systems FC-FC3 Manual de usuario descargar pdf (Pagina 36)

CONFIDENTIAL [AK8999A/AW/AD]

MS1600-E-00 2014/05

- 36 -

2) Finding the VOUT and VO Pins External Capacitance (Cap)

This section explains how the VOUT and VO pins external capacitance is defined.

The requirements for determining the VOUT and VO pins external capacitance values are the stabilization

time on power-up and noise characteristic.

2.1) VOUT Pin Output Voltage Stabilization Time

Note that depending on the VOUT and VO pins external capacitance values, the measurement values

(VOUT pin voltage) may contain errors upon power-up.

"99% Settling time (+ in the figure)" in the table below represents the analog stabilization time  in

the figure and the time required to settle down to 99% of the output voltage (0.1*VDD in this case)

according to the pressure applied during the period (+ in the figure).

The period  in the figure is 0.512msec (typ).

Subsequently, the output voltage will settle to 99% according to the pressure during period  in the

figure. When the VO pin capacitance is 1µF, the period  in the figure will settle within 672.4msec.

Settling time (period  in the figure) = -146[kΩ]*1[µF]*ln(1-99/100) = 672.4 [msec]

Therefore, the settling time up to 99% (period + in the figure) will be as follows:

99% settling time (period + in the figure) = 0.512[msec] +672.4[msec] = 672.912 [msec]

Referring to the previous calculation example, determine the stabilization time based on true terms of use:

Prerequisites: VO pin external capacitance: Cap（Cap[µF] typ., Cap*1.1[µF] worst）

VO pin internal resistance: Res（146[kΩ] typ., 190[kΩ] worst）

Period  in the figure: Time（0.512[msec] typ., 0.70[msec] worst）

Settling time (period  in the figure) = -Res*Cap*In(1-99/100)

99% settling time (period + in the figure) = Time + Settling time

VDD pin voltage

Sample timing



e.g. When sampling frequency is 8.33kHz and VOUT-VO

pin capacitance is 1μF.







VO&VOUT pin voltage

 -  Reference designators

: Sampling timing; this diagram represents 8.33kHz (0.12msec).

: Power-up rise time (VDD).

: Settling time for stable analog operation.

: Pressure signal detection time. This time depends on the VO pin external capacitance and the internal 146kΩ

resistance.

Hi-Z

1 2 ... 31 32 33 34 35 36 37 38 39 40 41 ... 67 68

Sin comentarios

Vicom Systems FC-FC3 Manual de usuario Pagina 36